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TPA3244D2DDWR Datasheet(PDF) 11 Page - Texas Instruments

No. de pieza TPA3244D2DDWR
Descripción Electrónicos  100W peak PurePath Ultra-HD Pad Down Class-D Amplifier
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TPA3244D2DDWR Datasheet(HTML) 11 Page - Texas Instruments

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TPA3244
www.ti.com
SLASEC6 – APRIL 2016
Product Folder Links: TPA3244
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Copyright © 2016, Texas Instruments Incorporated
(1)
Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.
7.4.1.6 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the
affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being
present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over
temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting
in device shutdown (OTE).
Table 6. Error Reporting
Fault/Event
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Output FETs
PVDD_X UVP
Voltage Fault
Global
FAULT pin
Self Clearing
Increase affected
supply voltage
HI-Z
VDD UVP
AVDD UVP
POR (DVDD UVP)
Power On Reset
Global
FAULT pin
Self Clearing
Allow DVDD to
rise
HI-Z
BST_X UVP
Voltage Fault
Channel (Half
Bridge)
None
Self Clearing
Allow BST cap to
recharge (lowside
ON, VDD 12V)
HighSide off
OTW
Thermal Warning
Global
OTW pin
Self Clearing
Cool below OTW
threshold
Normal operation
OTE
Thermal
Shutdown
Global
FAULT pin
Latched
Toggle RESET
HI-Z
OLP (CB3C>1.7ms)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
Latched OC
(47k
Ω<ROC_ADJ<68
k
Ω)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
CB3C
(22k
Ω<ROC_ADJ<30
k
Ω)
OC Limiting
Channel
None
Self Clearing
Reduce signal
level or remove
short
Flip state, cycle
by cycle at fs/3
Stuck at Fault(1)
No OSC_IO
activity in Slave
Mode
Global
None
Self Clearing
Resume OSC_IO
activity
HI-Z
7.4.1.7 Device Reset
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is
forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault.
To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of
FAULT.


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