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DAC128S085CIMT Datasheet(PDF) 10 Page - Texas Instruments |
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DAC128S085CIMT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 35 page DB15 SCLK DIN1 SYNC tDS tDH 1 2 15 16 DB15 DB0 DIN2/DOUT1 tDS DB0 DB0 tDH tSYNC tSS tCL tCH tSH 1 / fSCLK 1 2 15 16 DB15 DAC128S085 SNAS407H – AUGUST 2007 – REVISED APRIL 2015 www.ti.com AC and Timing Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, VREF1,2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are at TA = 25°C, unless otherwise specified. MIN(1) NOM MAX(1) UNIT 1 Data Set-Up Time prior to SCLK tDS ns Falling Edge. See Figure 1 TMIN ≤ TA ≤ TMAX 2.5 1 Data Hold Time after SCLK tDH ns Falling Edge. See Figure 1 TMIN ≤ TA ≤ TMAX 2.5 SYNC Hold Time after the 16th 0 1 / fSCLK - 3 tSH falling edge of SCLK. See ns TMIN ≤ TA ≤ TMAX 3 Figure 1 5 tSYNC SYNC High Time. See Figure 1 ns TMIN ≤ TA ≤ TMAX 15 Figure 1. Serial Timing Diagram 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC128S085 |
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