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FM24V01A-GTR Datasheet(PDF) 3 Page - Cypress Semiconductor

No. de pieza FM24V01A-GTR
Descripción Electrónicos  128-Kbit (16K 횞 8) Serial (I2C) F-RAM
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Fabricante Electrónico  CYPRESS [Cypress Semiconductor]
Página de inicio  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24V01A-GTR Datasheet(HTML) 3 Page - Cypress Semiconductor

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FM24V01A
Document Number: 001-90869 Rev. *H
Page 3 of 19
Pinout
Figure 1. 8-pin SOIC Pinout
WP
SCL
1
2
3
4
5
A0
8
7
6
VDD
SDA
A1
Top View
not to scale
VSS
A2
Pin Definitions
Pin Name
I/O Type
Description
A0-A2
Input
Device Select Address 0-2. These pins are used to select one of up to eight devices of the same type
on the same two-wire bus. To select the device, the address value on the three pins must match the
corresponding bits contained in the slave address. The address pins are pulled down internally.
SDA
Input/Output Serial Data Address. This is a bidirectional pin for the two-wire interface. It is open-drain and is
intended to be wire-AND'd with other devices on the two-wire bus. The input buffer incorporates a
Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An
external pull-up resistor is required.
SCL
Input
Serial Clock. The serial clock pin for the two-wire interface. Data is clocked out of the part on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
WP
Input
Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
VSS
Power supply Ground for the device. Must be connected to the ground of the system.
VDD
Power supply Power supply input to the device.


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