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TPS40001DGQ Datasheet(PDF) 11 Page - Texas Instruments |
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TPS40001DGQ Datasheet(HTML) 11 Page - Texas Instruments |
11 / 20 page TPS40000, TPS40001 TPS40002, TPS40003 TPS40004, TPS40005 SLUS507C − JANUARY 2002 − REVISED JUNE 2004 11 www.ti.com APPLICATION INFORMATION detailed description During each switching cycle, a comparator looks at the voltage across the top side MOSFET while it is on. This comparator is enabled after the SW node reaches a voltage greater than (VDD−1.2 V) followed by a 100-ns blanking time. If the voltage across that MOSFET exceeds a programmable threshold voltage, the current-switching pulse is terminated and a 3-bit counter is incremented by one count. If, during the switching cycle, the topside MOSFET voltage does not exceed a preset threshold, then this counter is decremented by one count. (The counter does not wrap around from 7 to 0 or from 0 to 7). If the counter reaches a full count of 7, the device declares that a fault condition exists at the output of the converter. In this fault state, HDRV is turned off and LDRV is turned on and the soft-start capacitor is discharged. The counter is decremented by one by the soft start capacitor (CSS) discharge. When the soft-start capacitor is fully discharged, the discharging circuit is turned off and the capacitor is allowed to charge up at the nominal charging rate. When the soft-start capacitor reaches about 700 mV, it is discharged again and the overcurrent counter is decremented by one count. The capacitor is charged and discharged, and the counter decremented until the count reaches zero (a total of six times). When this happens, the outputs are again enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting to restart. During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault until the soft-start cycle has been completed. It is possible to have a supply attempt to bring up a short circuit for the duration of the soft start period plus seven switching cycles. Power stage designs should take this into account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation. UDG−01145 0V VTS Overcurrent Cycle Normal Cycle Internal PWM External Main Drive Overcurrent Threshold Voltage (+) VTS (−) Figure 3. Switch Node Waveforms for Synchronous Buck Converter |
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