Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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CAT24C21UETE13 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
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CAT24C21UETE13 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
3 / 12 page CAT24C21 3 Doc. No. 1032, Rev. O A.C. CHARACTERISTICS VCC = 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. l o b m y Sr e t e m a r a Pn i Mx a Ms t i n U e d o M y l n o - t i m s n a r T T A A V K L C V m o r f d il a v t u p t u O5 . 0s µ T H G I H V h g i h K L C V6 . 0s µ T W O L V w o l K L C V3 . 1s µ T Z H V n o i t i s n a r t e d o M5 . 0s µ T U P V p u - r e w o p y l n o - t i m s n a r T0 s n s t i m i L e l c y C e t i r W & d a e R F L C S y c n e u q e r F k c o l C0 0 4z H k T I ) 1 ( , L C S t a t n a t s n o C e m i T n o i s s e r p p u S e s i o N s t u p n I A D S 0 0 1s n t A A t u O K C A d n a t u O a t a D A D S o t w o L L C S1 s µ t F U B ) 1 ( w e N a e r o f e B e e r F e b t s u M s u B e h t e m i T t r a t S n a C n o i s s i m s n a r T 2 . 1s µ t A T S : D H e m i T d l o H n o i t i d n o C t r a t S6 . 0s µ t W O L d o i r e P w o L k c o l C2 . 1s µ t H G I H d o i r e P h g i H k c o l C6 . 0s µ t A T S : U S e m i T p u t e S n o i t i d n o C t r a t S6 . 0s µ t T A D : D H e m i T d l o H n I a t a D0 s n t T A D : U S e m i T p u t e S n I a t a D0 5s n t R ) 1 ( e m i T e s i R L C S d n a A D S3 . 0s µ t F ) 1 ( e m i T ll a F L C S d n a A D S0 0 3s n t O T S : U S e m i T p u t e S n o i t i d n o C p o t S6 . 0s µ t H D e m i T d l o H t u O a t a D0 0 1s n g n i m i T p U - r e w o P ) 2 ( ) 1 ( t R U P n o i t a r e p O d a e R o t p u - r e w o P1 s m t W U P n o i t a r e p O e t i r W o t p u - r e w o P1 s m s t i m i L e l c y C e t i r W t R W e m i T e l c y C e t i r W5 s m The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/ erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. |
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