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CS9210 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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CS9210 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 39 page www.national.com 4 Revision 3.2 2.0 Signal Definitions This section defines the signals and external interface of the Geode CS9210. Figure 2-1 shows the pins organized by their functional groupings (internal test and electrical pins are not shown). 2.1 PIN ASSIGNMENTS The tables in this section use several common abbrevia- tions. Table 2-1 lists the mnemonics and their meanings. Figure 2-2 shows the pin assignment for the CS9210 with Tables 2-2 and 2-3 listing the pin assignments sorted by pin number and alphabetically by signal name, respec- tively. In Section 2.2 “Signal Descriptions” a description of each signal within its associated functional group is provided. Figure 2-1. CS9210 Signal Groups Table 2-1. Pin Type Definitions Mnemonic Definition I Standard input pin. I/O Bidirectional pin. O Totem-pole output. OD Open-drain output structure that allows multiple devices to share the pin in a wired-OR configuration PU Pull-up resistor PD Pull-down resistor smt Schmitt Trigger t/s Tri-state signal VDD (PWR) Power pin. VSS (GND) Ground pin # The "#" symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at a high volt- age level. RED[5:0] GREEN[5:0] BLUE[5:0] ENA_DISP ENA_VDDIN ENA_LCDIN DOTCLK FP_HSYNC FP_VSYNC SCLK SDIN SCS SDO LP SHFCLK FLM UD[11:0] LD[11:0] DISPOFF# FP_VDDEN FP_VCONEN MA_A[9:0] MD_A[15:0] MA_B[9:0] MD_B[15:0] OEA# OEB# RASA# RASB# LCASA# UCASA# LCASB# UCASB# RESET# Memory Interface Reset Interface Flat Panel Interface Pixel Port Interface Geode™ CS9210 Graphics Serial Interface WEA# WEB# Companion |
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