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DAC1219LCJ Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DAC1219LCJ Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 12 page  Application Hints The DAC1218 and DAC1219 are pin-for-pin compatible with the DAC1220 series but feature 12 and 11-bit linearity spec- ifications To preserve this degree of accuracy care must be taken in the selection and adjustments of the output am- plifier and reference voltage Careful PC board layout is im- portant with emphasis made on compactness of compo- nents to prevent inadvertent noise pickup and utilization of single point grounding and supply distribution 10 BASIC CIRCUIT DESCRIPTION Figure 1 illustrates the R-2R current switching ladder net- work used in the DAC1218 and DAC1219 As a function of the logic state of each digital input the binarily weighted current in each leg of the ladder is switched to either IOUT1 or IOUT2 The voltage potential at IOUT1 and IOUT2 must be at zero volts to keep the current in each leg the same inde- pendent of the switch state The switches operate with a small voltage drop across them and can therefore conduct currents of either polarity This permits the reference to be positive or negative thereby allowing 4-quadrant multiplication by the digital input word The reference can be a stable DC source or a bipolar AC signal within the range of g10V for specified accuracy with an absolute maximum range of g25V The reference can also exceed the applied VCC of the DAC The maximum output current from either IOUT1 or IOUT2 is equal to VREF(max) R 4095 4096 J where R is the reference input resistance (typically 15 kX) A high level on any digital input steers current to IOUT1 and a low level steers current to IOUT2 20 CREATING A UNIPOLAR OUTPUT VOLTAGE (A DIGITAL ATTENUATOR) To generate an output voltage and keep the potential at the current output terminals at 0V an op amp current to voltage converter is used As shown in Figure 2 the current from IOUT1 flows through the feedback resistor forcing a propor- tional voltage at the amplifier output The voltage at IOUT1 is held at a virtual ground potential The feedback resistor is provided on the chip and should always be used as it matches and tracks the R value of the R-2R ladder The output voltage is the opposite polarity of the applied refer- ence voltage 21 Amplifier Considerations To maintain linearity of the output voltage with changing digital input codes the input offset voltage of the amplifier must be nulled The resistance from IOUT1 to ground (RIOUT1) varies non-linearly with the applied digital code from a minimum of R with all ones applied to the input to near % with an all zeros code Any offset voltage between the amplifier inputs appears at the output with a gain of 1 a RF RIOUT1 Since RIOUT1 varies with the input code any offset will de- grade output linearity (See Note 4 of Electrical Characteris- tics) If the desired amplifier does not have offset balancing pins available (it could be part of a dual or quad package) the nulling circuit of Figure 3 can be used The voltage at the non-inverting input will be set to b VOS initially to force the inverting input to 0V The common technique of summing current into the amplifier summing junction cannot be used as it directly introduces a zero code output current error TLH5691 – 4 Note Switches shown in digital high state FIGURE 1 The R-2R Current Switching Ladder Network 5 |
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