CS1112YDWFR24 datasheet(4/12 Pages) ONSEMI

No. de pieza	CS1112YDWFR24

Descripción Electrónicos	Quad Power Output Driver

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ELECTRICAL CHARACTERISTICS (continued) (9.0 V < VPWR < 17 V, 4.5 V < VDD < 5.5 V, –40°C < TJ < 125°C,

5.5 V < VPWR < 25 V, (Outputs Functional); unless otherwise specified.)

Characteristic

Unit

Max

Typ

Min

Test Conditions

Serial Peripheral Interface

VPWR = 14 V

SCLK Clock Period

CO = 200 pF

250

–

ns

MAX Input Capacitance

SI, SCLK, Note 1.

–

12

pF

VOUT High

SO, IOH = 1.0 mA

VDD – 1.0

–

V

VOUT Low

SO, IOL = 1.0 mA

–

0.5

V

SCLK High Time

FSCLK = 4.0 MHz, SCLK = 2.0 V to 2.0 V

(see Figure 1)

125

–

ns

SCLK Low Time

FSCLK = 4.0 MHz, SCLK = 0.8 V to 0.8 V

(see Figure 1)

125

–

ns

SI Setup Time

SI = 0.8 V/2.0 V to SCLK = 2.0 V at 4.0 MHz;

Note 1. (see Figure 1)

25

–

ns

SI Hold Time

SCLK = 2.0 V to SI = 0.8 V/2.0 V at 4.0 MHz;

Note 1. (see Figure 1)

25

–

ns

SO Rise Time

CLD = 200 pF (0.1 VDD to 0.9 VDD);

Note 1.

–

25

50

ns

SO Fall Time

CLD = 200 pF (0.9 VDD to 0.1 VDD);

Note 1.

–

50

ns

CSB Setup Time

CSB = 0.8 V to SCLK = 2.0 V

(see Figure 1) Note 1.

60

–

ns

CSB Hold Time

SCLK = 0.8 V to CSB = 2.0 V

(see Figure 1) Note 1.

75

–

ns

SO Delay Time

SCLK = 0.8 V to SO Data Valid, VDD = 5.0 V

CLD = 200 pF at 4.0 MHz

(see Figure 1); Note 1.

–

65

125

ns

Xfer Delay Time

CSB rising edge to next falling edge.

Note 1.

1.0

–

µs

1. Guaranteed by design.

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

24 Lead SOIC

PIN SYMBOL

FUNCTION

1

VDD

Input voltage to bias logic and control circuitry.

2

VPWR

Input voltage to bias gate drive circuitry.

3

OUT0

Open drain output one.

4

IN0

Parallel input one.

5, 6, 7, 8

17, 18, 19, 20

GND

Ground Reference.

9

IN1

Parallel input two.

10

OUT1

Open drain output two.

11

SI

SPI serial input.

12

CSB

SPI active low chip select.

13

SCLK

SPI clock input.

14

SO

SPI serial output.

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CS1112YDWFR24 Datasheet(PDF) 4 Page - ON Semiconductor

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