CS5211EDR14 datasheet(3/16 Pages) ONSEMI

No. de pieza	CS5211EDR14

Descripción Electrónicos	Low Voltage Synchronous Buck Controller

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3

MAXIMUM RATINGS (continued)

Pin Name

ISINK

ISOURCE

VMIN

VMAX

Pin Symbol

Fast Feedback Input

VFFB

6.0 V

–0.3 V

1.0 mA

High–Side FET Driver

GATE(H)

20 V

–0.3 V

–2.0 V for 50 ns

1.5 A Peak

200 mA DC

1.5 A Peak

200 mA DC

Low–Side FET Driver

GATE(L)

16 V

–0.3 V

–2.0 V for 50 ns

1.5 A Peak

200 mA DC

1.5 A Peak

200 mA DC

Positive Current Sense

IS+

6.0 V

–0.3 V

1.0 mA

Negative Current Sense

IS–

6.0 V

–0.3 V

1.0 mA

Power Ground

PGND

0.3 V

–0.3 V

1.5 A Peak, 200 mA DC

N/A

Logic Ground

LGND

0 V

100 mA

N/A

Sense Ground

SGND

0.3 V

–0.3 V

1.0 mA

ELECTRICAL CHARACTERISTICS (–40

°C < TA < 85°C; –40°C < TJ < 125°C; 4.5 V < VCC, VC < 14 V;

7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 µF, unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Error Amplifier

VFB Bias Current

VFB = 0 V

–

0.1

1.0

µA

COMP Source Current

VFB = 0.8 V

15

30

60

µA

COMP SINK Current

VFB = 1.2 V

15

30

60

µA

Open Loop Gain

–

98

–

dB

Unity Gain Bandwidth

C = 0.1

µF

–

50

–

kHz

PSRR @ 1.0 kHz

–

70

–

dB

Output Transconductance

–

32

–

mmho

Output Impedance

–

2.5

–

M

Ω

Reference Voltage

–0.1 V < SGND < 0.1 V,

COMP = VFB, Measure VFB to SGND

0.977

0.992

1.007

V

COMP Max Voltage

VFB = 0.8 V

2.5

3.0

–

V

COMP Min Voltage

VFB = 1.2 V

–

0.1

0.2

V

GATE(H) and GATE(L)

High Voltage (AC)

GATE(L),

GATE(H)

0.5 nF < CGATE(H) = CGATE(L) < 10 nF

VC – 0.5

BST – 0.5

–

V

Low Voltage (AC)

GATE(L) or GATE(H)

0.5 nF < CGATE(H); CGATE(L) < 10 nF

–

0.5

V

Rise Time

VC = BST = 10 V, Measure:

1.0 V < GATE(L) < 9.0 V,

1.0 V < GATE(H) < 9.0 V

–

40

80

ns

Fall Time

VC = BST = 10 V, Measure:

1.0 V < GATE(L) < 9.0 V,

1.0 V < GATE(H) < 9.0 V

–

40

80

ns

GATE(H) to GATE(L) Delay

GATE(H) < 2.0 V, GATE(L) > 2.0 V

40

70

110

ns

GATE(L) to GATE(H) Delay

GATE(L) < 2.0 V, GATE(H) > 2.0 V

40

70

110

ns

GATE(H)/(L) Pull–Down

Resistance to PGND

20

50

115

K

Ω

2. Guaranteed by design. Not tested in production.

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