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GS72116AT-8I Datasheet(PDF) 1 Page - GSI Technology |
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GS72116AT-8I Datasheet(HTML) 1 Page - GSI Technology |
1 / 18 page Rev: 1.04a 10/2002 1/18 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS72116ATP/J/T/U 128K x 16 2Mb Asynchronous SRAM 7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS SOJ, TSOP, FP-BGA, TQFP Commercial Temp Industrial Temp Features • Fast access time: 7, 8, 10, 12 ns • CMOS low power operation: 145/125/100/85 mA at minimum cycle time • Single 3.3 V power supply • All inputs and outputs are TTL-compatible • Byte control • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up J: 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package T: 10 mm x 10 mm, 44-pin TQFP U: 6 mm x 8 mm Fine Pitch Ball Grid Array package Description The GS72116A is a high speed CMOS Static RAM organized as 131,072 words by 16 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a sin- gle 3.3 V power supply and all inputs and outputs are TTL- compatible. The GS72116A is available in a 6 mm x 8 mm Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as well as in 400 mil SOJ and 400 mil TSOP Type-II packages. Pin Descriptions SOJ 128K x 16-Pin Configuration Package J Symbol Description A0–A16 Address input DQ1–DQ16 Data input/output CE Chip enable input LB Lower byte enable input (DQ1 to DQ8) UB Upper byte enable input (DQ9 to DQ16) WE Write enable input OE Output enable input VDD +3.3 V power supply VSS Ground NC No connect 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 Top view 21 22 24 23 A12 A11 44-pin SOJ NC A16 |
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