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ADC10D1500 Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza ADC10D1500
Descripción Electrónicos  Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADC10D1500 Datasheet(HTML) 7 Page - Texas Instruments

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GND
VA
GND
VA
VA
A GND
-
+
100:
100:
VA
AGND
VA
AGND
100
VBIAS
50k
50k
ADC10D1000, ADC10D1500
www.ti.com
SNAS462Q – OCTOBER 2008 – REVISED MARCH 2013
Table 3. Analog Front-End and Clock Balls (continued)
Ball No.
Name
Equivalent Circuit
Description
Reference Clock Input. When the AutoSync
feature is active, and the ADC10D1000/1500 is in
Slave Mode, the internal divided clocks are
Y4/W5
RCLK+/-
synchronized with respect to this input clock. The
delay on this clock may be adjusted when
synchronizing multiple ADCs. This feature is
available in ECM via Control Register (Addr: Eh).
Reference Clock Output 1 and 2. These signals
provide a reference clock at a rate of CLK/4, when
enabled, independently of whether the ADC is in
Master or Slave Mode. They are used to drive the
RCLK of another ADC10D1000/1500, to enable
automatic synchronization for multiple ADCs
Y5/U6
RCOut1+/-
(AutoSync feature). The impedance of each trace
V6/V7
RCOut2+/-
from RCOut1 and RCOut2 to the RCLK of another
ADC10D1000/1500 should be 100
Ω differential.
Having two clock outputs allows the auto-
synchronization to propagate as a binary tree. Use
the DOC Bit (Addr: Eh, Bit 1) to enable/ disable
this feature; default is disabled.
Table 4. Control and Status Balls
Ball No.
Name
Equivalent Circuit
Description
Dual Edge Sampling (DES) Mode select. In the
Non-Extended Control Mode (Non-ECM), when
this input is set to logic-high, the DES Mode of
operation is selected, meaning that the VinI input
is sampled by both channels in a time-interleaved
manner. The VinQ input is ignored. When this
V5
DES
input is set to logic-low, the device is in Non-DES
Mode, i.e. the I- and Q-channels operate
independently. In the Extended Control Mode
(ECM), this input is ignored and DES Mode
selection is controlled through the Control Register
by the DES Bit (Addr: 0h, Bit 7); default is Non-
DES Mode operation.
Calibration Delay select. By setting this input logic-
high or logic-low, the user can select the device to
wait a longer or shorter amount of time,
V4
CalDly
respectively, before the automatic power-on self-
calibration is initiated. This feature is pin-controlled
only and is always active during ECM and Non-
ECM.
Copyright © 2008–2013, Texas Instruments Incorporated
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