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ADC101C021 Datasheet(PDF) 9 Page - Texas Instruments

No. de pieza ADC101C021
Descripción Electrónicos  10-Bit Analog-to-Digital Converter
Download  44 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADC101C021 Datasheet(HTML) 9 Page - Texas Instruments

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ADC101C021, ADC101C027
www.ti.com
SNAS446D – FEBRUARY 2008 – REVISED FEBRUARY 2013
A.C. and Timing Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are
at TA = 25°C, unless otherwise specified.
Typical
Limits
Units
Symbol
Parameter
Conditions (1)
(2)
(2) (1)
(Limits)
Standard Mode
4.0
us (min)
tSU;STO
Setup time for a stop condition
Fast Mode
0.6
us (min)
High Speed Mode
160
ns (min)
Standard Mode
1000
ns (max)
20+0.1Cb
ns (min)
Fast Mode
300
ns (max)
trDA
Rise time of SDA signal
10
ns (min)
High Speed Mode, Cb = 100pF
80
ns (max)
20
ns (min)
High Speed Mode, Cb = 400pF
160
ns (max)
Standard Mode
250
ns (max)
20+0.1Cb
ns (min)
Fast Mode
250
ns (max)
tfDA
Fall time of SDA signal
10
ns (min)
High Speed Mode, Cb = 100pF
80
ns (max)
20
ns (min)
High Speed Mode, Cb = 400pF
160
ns (max)
Standard Mode
1000
ns (max)
20+0.1Cb
ns (min)
Fast Mode
300
ns (max)
trCL
Rise time of SCL signal
10
ns (min)
High Speed Mode, Cb = 100pF
40
ns (max)
20
ns (min)
High Speed Mode, Cb = 400pF
80
ns (max)
Standard Mode
1000
ns (max)
20+0.1Cb
ns (min)
Fast Mode
300
ns (max)
Rise time of SCL signal after a
trCL1
repeated start condition and after an
10
ns (min)
High Speed Mode, Cb = 100pF
acknowledge bit.
80
ns (max)
20
ns (min)
High Speed Mode, Cb = 400pF
160
ns (max)
Standard Mode
300
ns (max)
20+0.1Cb
ns (min)
Fast Mode
300
ns (max)
tfCL
Fall time of a SCL signal
10
ns (min)
High Speed Mode, Cb = 100pF
40
ns (max)
20
ns (min)
High Speed Mode, Cb = 400pF
80
ns (max)
Capacitive load for each bus line (SCL
Cb
400
pF (max)
and SDA)
Pulse Width of spike suppressed
Fast Mode
50
ns (max)
tSP
(4)
High Speed Mode
10
ns (max)
(4)
Spike suppression filtering on SCL and SDA will suppress spikes that are less than 50ns for standard and fast modes, and less than
10ns for hs-mode.
Copyright © 2008–2013, Texas Instruments Incorporated
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