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ADC08DL500 Datasheet(PDF) 2 Page - Texas Instruments |
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ADC08DL500 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 57 page VREF CLK/2 8-BIT ADC1 VINI+ VINI- DCLK+ DCLK- Data Bus Output 16 LVDS Pairs Selectable DEMUX OR/DCLK2 Control Logic 8-BIT ADC2 Data Bus Output 16 LVDS Pairs 3 CalRun + - + - S/H S/H VBG CLK+ CLK- Control Inputs Serial Interface DEMUX DI LATCH Selectable DEMUX LATCH VINQ+ VINQ- 8 8 Output Clock Generator 2 + + DId DQ DQd ADC08DL500 SNAS495C – MARCH 2011 – REVISED MARCH 2011 www.ti.com Block Diagram 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: ADC08DL500 |
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