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74AC11286N Datasheet(PDF) 1 Page - Texas Instruments |
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74AC11286N Datasheet(HTML) 1 Page - Texas Instruments |
1 / 9 page 74AC11286 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS SCAS068A – AUGUST 1988 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 2–1 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Direct Bus Connection for Parity Generation or for Checking by Using the Parity I/O Port • Flow-Through Architecture Optimizes PCB Layout • Center-Pin V CC and GND Configurations Minimize High-Speed Switching Noise • EPICt (Enhanced-Performance Implanted CMOS) 1- mm Process • 500-mA Typical Latch-Up Immunity at 125 °C • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading. The XMIT control input is implemented specifically to accommodate cascading. When the XMIT is low, the parity tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels. When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level. The I/O control circuitry was designed so that the I/O port will remain in the high-impedance state during power up or power down to prevent bus glitches. The 74AC11286 is characterized for operation from – 40 °C to 85°C. FUNCTION TABLE NUMBER OF INPUTS (A THRU I) THAT ARE HIGH XMIT INPUT PARITY I/O PARITY ERROR OUTPUT 0, 2, 4, 6, 8 l H H 1, 3, 5, 7, 9 l L H 02468 h h H 0, 2, 4, 6, 8 h l L 13579 h h L 1, 3, 5, 7, 9 h l H h — high input level l — low input level H — high output level L — low output level 1 2 3 4 5 6 7 14 13 12 11 10 9 8 B A PARITY I/O GND PARITY ERROR XMIT I C D E VCC F G H D OR N PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. EPIC is a trademark of Texas Instruments Incorporated. |
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