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8V182512IDGGREP Datasheet(PDF) 1 Page - Texas Instruments

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No. de pieza 8V182512IDGGREP
Descripción Electrónicos  3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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8V182512IDGGREP Datasheet(HTML) 1 Page - Texas Instruments

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SN74LVTH18512EP, SN74LVTH182512EP
3.3V ABT SCAN TEST DEVICES
WITH 18BIT UNIVERSAL BUS TRANSCEIVERS
SCBS790 − NOVEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Members of the Texas Instruments
SCOPE
 Family of Testability Products
D Members of the Texas Instruments
Widebus
 Family
D State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D B-Port Outputs of SN74LVTH182512 Device
Has Equivalent 25-
Ω Series Resistors, So
No External Resistors Are Required
D SCOPE  Instruction Set
− IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
− Parallel-Signature Analysis at Inputs
− Pseudo-Random Pattern Generation
From Outputs
− Sample Inputs/Toggle Outputs
− Binary Count From Outputs
− Device Identification
− Even-Parity Opcodes
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
Copyright
 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and UBT are trademarks of Texas Instruments.
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1CLKAB
1LEAB
1OEAB
1A1
1A2
GND
1A3
1A4
1A5
VCC
1A6
1A7
1A8
GND
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
2A9
GND
2OEAB
2LEAB
2CLKAB
TDO
TMS
1CLKBA
1LEBA
1OEBA
1B1
1B2
GND
1B3
1B4
1B5
VCC
1B6
1B7
1B8
GND
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
2B9
GND
2OEBA
2LEBA
2CLKBA
TDI
TCK
DGG PACKAGE
(TOP VIEW)


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