74AC11898

10BIT PARALLELOUT SERIAL SHIFT REGISTER

SCAS143 − OCTOBER 1990 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Copyright

2−1

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

The 74AC11898 features AND-gated serial inputs and an asynchronous clear. The gated serial inputs

(A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets

the first flip-flop to the low level on the rising edge of the next clock pulse. A high-level input enables the other

input, which then determines the state of the first flip-flop. Data at the serial inputs may be changed while the

clock is high or low provided the minimum setup and hold time requirements are met. Clocking occurs on the

low-to-high transition of the clock input.

The 74AC11898 is characterized for operation from − 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

CLK

A

B

QA

QB

...

QJ

L

X

X

X

L

L

L

H

LX

X

QA0

QB0

QJO

H

↑

HHH

QAN

QIN

H

↑

LXL

QAN

QIN

H

↑

X

L

L

QAN

QIN

H = high level (steady state)

X = irrelevant (any input, including transitions)

↑ = transition from low to high level

QA0, QB0, QJ0 = the level of QA, QB, QJ respectively, before the

indicated steady-state input conditions were established.

Qn, Qin = the level or QA or QJ before the most recent ↑ transition

of the clock; indicates a one-bit shift.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

DW OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

GND

GND

GND

CLR

A

B

CLK

EPIC is a trademark of Texas Instruments Incorporated.