74ACT11181

ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR

SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

2−2

description

The 74ACT11181 is an arithmetic logic unit (ALU)/function generator that has a complexity of 75 equivalent

gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown

in Tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include

addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal

carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead

scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade

outputs G and P for the four bits in the package. When used in conjunction with the ’ACT11882 full carry

look-ahead circuits, high-speed arithmetic operations can be performed. The method of cascading ’ACT11882

circuits with these ALUs to provide multilevel full-carry look-ahead operation is illustrated under signal

designations.

the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be

performed without external circuitry.

The 74ACT11181 will accommodate active-high or active-low data if the pin designations are interpreted as

follows:

PACKAGE

PIN NUMBERS AND DESIGNATIONS

DW, JT, or NT

25

26

27

28

19

20

23

24

11

10

5

4

1

14

12

13

FK

4

5

6

7

26

27

2

3

18

17

12

11

8

2

19

20

Active-low data

(Table 1)

A3

A2

A1

A0

B3

B2

B1

B0

F3

F2

F1

F0

Cn

Cn+4

P

G

Active-high data

(Table 2)

A3

A2

A1

A0

B3

B2

B1

B0

F3

F2

F1

F0

Cn

Cn+4

X

Y

Subtraction is accomplished by 1’s complement addition where the 1’s complement of the subtrahend is

generated internally. The resultant output is A − B − 1, which requires an end-around or forced carry to provide

A− B.

The 74ACT11181 can also be used as a comparator. The A = B output is internally decoded from the function

outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will

assume a high level to indicate equality (A = B). When performing this comparison, the ALU must be in the

information. Again, the ALU must be placed in the subtract mode by placing the function select inputs S3, S2,

S1, S0 at L, H, H, L, respectively.

INPUT Cn

OUTPUT Cn+4

ACTIVE-LOW DATA

ACTIVE-HIGH DATA

INPUT Cn

OUTPUT Cn+4

ACTIVE-LOW DATA

(FIGURE 1)

ACTIVE-HIGH DATA

(FIGURE 2)

H

H

A

≥ B

A

≤ B

H

L

A<B

A>B

L

H

A>B

A<B

L

L

A

≤ B

A

≥ B

These circuits have been designed not only to incorporate all of the designer’s requirements for arithmetic

operation but also to provide 16 possible functions of two Boolean variables without using external circuitry.

These logic functions are selected using the four function-select inputs (S0, S1, S2, S3) with the mode-control

input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and

include exclusive-OR, NAND, AND, NOR, and OR functions.