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74ACT11112DR Datasheet(PDF) 4 Page - Texas Instruments |
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74ACT11112DR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 8 page 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–4 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 25°C MIN MAX UNIT PARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN MAX UNIT fmax 125 125 MHz tPLH PRE or CLR QorQ 1.5 3.6 6.3 1.5 6.8 ns tPHL PRE or CLR Q or Q 1.5 4.6 7.4 1.5 8 ns tPLH CLK QorQ 1.5 4.2 7 1.5 7.7 ns tPHL CLK Q or Q 1.5 4.7 7.4 1.5 8.4 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per flip-flop CL = 50 pF, f = 1 MHz 39 pF PARAMETER MEASUREMENT INFORMATION 50% VCC 1.5 V 1.5 V 1.5 V 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS Data Input tPLH tPHL tPHL tPLH VOH VOH VOL VOL 1.5 V 1.5 V 3 V 0 V 50% VCC 50% VCC Input (see Note B) Out-of-Phase Output In-Phase Output Timing Input (see Note B) 50% VCC VOLTAGE WAVEFORMS 3 V 0 V 1.5 V 1.5 V tw VOLTAGE WAVEFORMS Input LOAD CIRCUIT From Output Under Test CL = 50 pF (see Note A) 500 Ω NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms |
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