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AM1802BZCED3 Datasheet(PDF) 3 Page - Texas Instruments |
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AM1802BZCED3 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 182 page Switched Central Resource (SCR) 16KB I-Cache 16KB D-Cache 4KB ETB ARM926EJ-S CPU With MMU ARM Subsystem JTAG Interface System Control Input Clock(s) 64KB ROM 8KB RAM (Vector Table) Power/Sleep Controller Pin Multiplexing PLL/Clock Generator w/OSC General- Purpose Timer (x3) Serial Interfaces Audio Ports McASP w/FIFO DMA Peripherals Internal Memory 128KB RAM External Memory Interfaces Connectivity EDMA3 (x2) EMIFA(8b/16B) NAND/Flash 16b SDRAM DDR2/MDDR Controller RTC/ 32-kHz OSC I C 2 (x1) SPI (x2) UART (x3) EMAC 10/100 (MII/RMII) MDIO USB2.0 OTG Ctlr PHY MMC/SD (8b) (x1) Memory Protection AM1802 www.ti.com SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014 1.4 Functional Block Diagram Figure 1-1 shows the functional block diagram of the device. Figure 1-1. Functional Block Diagram Copyright © 2010–2014, Texas Instruments Incorporated AM1802 ARM Microprocessor 3 Submit Documentation Feedback Product Folder Links: AM1802 |
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