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74ACT11867NT Datasheet(PDF) 1 Page - Texas Instruments |
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74ACT11867NT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 11 page 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Inputs Are TTL-Voltage Compatible D Asynchronous Clear D Fully Independent Clock Circuit Simplifies Use D Flow-Through Architecture Optimizes PCB Layout D Center-Pin V CC and GND Configurations Minimize High-Speed Switching Noise D EPIC™ (Enhanced-Performance Implanted CMOS) 1- μm Process D 500-mA Typical Latch-Up Immunity at 125 °C description The 74ACT11867 is a synchronous presettable binary counter featuring an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform. The counters are fully programmable; that is, the outputs can each be preset to either logic level. The load-mode circuitry allows parallel loading of the cascaded counters. As loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock rising edge. The carry look-ahead circuitry is provided for cascading counters for n-bit synchronous applications without additional gating. This is done with two count-enable inputs and a carry output. Both count-enable (ENP and ENT) inputs must be low to count. The direction of the count is determined by the levels of the select (S0 and S1) inputs (see the function table). Input ENT is fed forward to enable the ripple-carry (RCO) output. RCO then produces a low-level pulse while the count is zero (all outputs low) when counting down or 255 during counting up (all outputs high). This low-level overflow carry pulse can be used to enable successive cascaded stages. Transitions at ENP and ENT are allowed regardless of the level of the clock input. These counters feature a fully independent clock circuit. Whenever ENP and/or ENT is taken high, RCO either goes high or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The 74ACT11867 is characterized for operation from −40 °C to 85°C. Copyright © 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. EPIC is a trademark of Texas Instruments Incorporated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. QA QB QC QD QE GND GND GND GND QF QG QH RCO CLK DW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A B C D E F VCC VCC G H ENP ENT S0 S1 |
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