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SN74GTLPH306 Datasheet(PDF) 1 Page - Texas Instruments

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No. de pieza SN74GTLPH306
Descripción Electrónicos  8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
Download  17 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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SN74GTLPH306 Datasheet(HTML) 1 Page - Texas Instruments

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FEATURES
DGV, DW, OR PW PACKAGE
(TOP VIEW)
OE
VCC
A1
A2
A3
A4
GND
A5
A6
A7
A8
GND
DIR
VREF
B1
B2
B3
B4
GND
B5
B6
B7
B8
GND
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DESCRIPTION/ORDERING INFORMATION
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED APRIL 2005
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on A-Port Data Inputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard
LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input
threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and
TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models.
The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance
down to 19
Ω.
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD
8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and
VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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