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74LVC2G38 Datasheet(PDF) 8 Page - NXP Semiconductors |
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74LVC2G38 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 15 page 2004 Oct 18 8 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 Note 1. All typical values are measured at Tamb =25 °C. Tamb = −40 °C to +125 °C VIH HIGH-level input voltage 1.65 to 1.95 0.65 × V CC −− V 2.3 to 2.7 1.7 −− V 2.7 to 3.6 2.0 −− V 4.5 to 5.5 0.7 × V CC −− V VIL LOW-level input voltage 1.65 to 1.95 −− 0.35 × VCC V 2.3 to 2.7 −− 0.7 V 2.7 to 3.6 −− 0.8 V 4.5 to 5.5 −− 0.3 × VCC V VOL LOW-level output voltage VI =VIH or VIL IO = 100 µA 1.65 to 5.5 −− 0.1 V IO = 4 mA 1.65 −− 0.70 V IO = 8 mA 2.3 −− 0.45 V IO = 12 mA 2.7 −− 0.60 V IO = 24 mA 3.0 −− 0.80 V IO = 32 mA 4.5 −− 0.80 V ILI input leakage current VI = 5.5 V or GND 5.5 −− ±20 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 −− ±20 µA ICC quiescent supply current VI =VCC or GND; IO =0A 5.5 −− 40 µA ∆ICC additional quiescent supply current per pin VI =VCC − 0.6 V; IO =0A 2.3 to 5.5 −− 5000 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) |
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