CD74AC174

HEX D-TYPE FLIP-FLOP

WITH CLEAR

SCHS346 – APRIL 2003

1

POST OFFICE BOX 655303

and Balanced Noise Immunity at 30% of the

Supply Voltage

Outputs

Significantly Reduced Power Consumption

– Fanout to 15 F Devices

Circuit Design

MIL-STD-883, Method 3015

– Buffer/Storage Registers

– Shift Registers

description/ordering information

The CD74AC174 is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input and is designed for

Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low

level, the D input has no effect at the output.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E

Tube

CD74AC174E

CD74AC174E

–55

°C to 125°C

SOIC

M

Tube

CD74AC174M

AC174M

SOIC – M

Tape and reel

CD74AC174M96

AC174M

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR

CLK

D

Q

L

X

X

L

H

↑

HH

H

↑

LL

H

L

X

Q0

E OR M PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

1Q

1D

2D

2Q

3D

3Q

GND

6Q

6D

5D

5Q

4D

4Q

CLK

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

 2003, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.