CDCE913-Q1 datasheet(6/27 Pages) TI1

No. de pieza	CDCE913-Q1

Descripción Electrónicos	Programmable 1-PLL VCXO Clock Synthesizer

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Fabricante Electrónico	TI1 [Texas Instruments]

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CDCE913-Q1

CDCEL913-Q1

SCAS918A – JUNE 2013

www.ti.com

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating free-air temperature

MIN

NOM

MAX

UNIT

CLK_IN REQUIREMENTS

PLL bypass mode

0

160

fCLK

LVCMOS clock input frequency

MHz

PLL mode

8

160

tr, tf

Rise and fall time CLK signal (20% to 80%)

3

ns

Duty cycle CLK at VDD 2

40%

60%

STANDARD

FAST

MODE

UNIT

MIN

MAX

MIN

MAX

SDA/SCL TIMING REQUIREMENTS (see Figure 12)

fSCL

SCL clock frequency

0

100

0

400

kHz

tsu(START)

START setup time (SCL high before SDA low)

4.7

0.6

μs

th(START)

START hold time (SCL low after SDA low)

4

0.6

μs

tw(SCLL)

SCL low-pulse duration

4.7

1.3

μs

tw(SCLH)

SCL high-pulse duration

4

0.6

μs

th(SDA)

SDA hold time (SDA valid after SCL low)

0

3.45

0

0.9

μs

tsu(SDA)

SDA setup time

250

100

ns

tr

SCL/SDA input rise time

1000

300

ns

tf

SCL/SDA input fall time

300

ns

tsu(STOP)

STOP setup time

4

0.6

μs

tBUS

Bus free time between a STOP and START condition

4.7

1.3

μs

6

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Product Folder Links: CDCE913-Q1 CDCEL913-Q1

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