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Not Recommended for New Designs

CDCF5801

SCAS698F – SEPTEMBER 2003 – REVISED APRIL 2006

The CDCF5801 provides clock multiplication and division from a reference clock (REFCLK) signal. The device is

optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and

post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating

CLKOUT/CLOUTKB frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK)

ranging from 12.5 MHz to 240 MHz. See Table 1 for detailed frequency support. The selection of pins MULT[0:1]

and P[1:2] determines the multiplication value of 1, 2, 4, or 8. The CDCF5801 offers several power-down/

high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the

CDCF5801 is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the

voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to

generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a

differential output signal suitable for LVDS, LVPECL, or HSTL/SSTL signaling. The CDCF5801 is characterized

for operation over free-air temperatures of -40

°C to 85°C.

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