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CDCFR83ADBQ Datasheet(PDF) 2 Page - Texas Instruments |
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CDCFR83ADBQ Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page www.ti.com Bypass MUX Test MUX B A PLL Phase Aligner PACLK PLLCLK ByPCLK CLK CLKB REFCLK φD SYNCLKN PCLKM MULT0 MULT1 2 PWRDWNB S0 S1 S2 STOPB CDCFR83A SCAS812 – AUGUST 2005 User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing. The CDCFR83A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. The CDCFR83A is characterized for operation over free-air temperatures of –40 °C to 85°C. FUNCTIONAL BLOCK DIAGRAM FUNCTION TABLE(1) MODE S0 S1 S2 CLK CLKB Normal 0 0 0 Phase aligned clock Phase aligned clock B Bypass 1 0 0 PLLCLK PLLCLKB Test 1 1 0 REFCLK REFCLKB Output test (OE) 0 1 x Hi-Z Hi-Z Reserved 0 0 1 – – Reserved 1 0 1 – – Reserved 1 1 1 Hi-Z Hi-Z (1) X = don't care, Hi-Z = high impedance 2 |
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