CDCM6208V2G datasheet(5/88 Pages) TI1

No. de pieza	CDCM6208V2G

Descripción Electrónicos	CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Fabricante Electrónico	TI1 [Texas Instruments]

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CDCM6208V2G

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SNAS682 – MARCH 2016

Product Folder Links: CDCM6208V2G

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Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NAME

NO.

(2)

Note: the device cannot be programmed in I2C while RESETN is held low.

SDO/AD0/PIN2

3

Output/

Input

LVCMOS out

LVCMOS in

no pull resistor

SDO: SPI Serial Data

AD0: I2C Address Offset Bit 0 input

PIN2: Control pin 2 in pin mode

SCS/AD1/PIN 3

4

Input

LVCMOS

no pull resistor

SCS: SPI Latch Enable

AD1: I2C Address Offset Bit 1 input

PIN3: Control pin 3 in pin mode

SCL/PIN4

5

Input

LVCMOS

no pull resistor

SCL: SPI/I2C Clock

PIN4: Control pin 4 in pin mode

RESETN/PWR

44

Input

LVCMOS

50kΩ pull-up

In SPI/I2C programming mode, external RESETN signal (active low).

RESETN = V IL: device in reset (registers values are retained)

RESETN = V IH: device active. The device can be programmed via SPI while

RESETN is held low (this is useful to avoid any false output frequencies at power

up). (2)

In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1

= 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not

possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3

V.

REG_CAP

40

Output

Analog

Regulator Capacitor; connect a 10 µF cap with ESR below 1 Ω to GND at

frequencies above 100 kHz

PDN

43

Input

LVCMOS

50kΩ pull-up

Power Down Active low. When PDN = VIH is normal operation. When PDN = VIL, the

device is disabled and current consumption minimized. Exiting power down resets

the entire device and defaults all registers. It is recommended to connect a capacitor

to GND to hold the device in power-down until the digital and PLL related power

supplies are stable. See section on power down in the application section.

SYNCN

42

Input

LVCMOS

50kΩ pull-up

Active low. Device outputs are synchronized on a low-to-high transition on the

SYNCN pin. SYNCN held low disables all outputs.

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CDCM6208V2G Datasheet(PDF) 5 Page - Texas Instruments

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