CDCM1802RGTRG4 datasheet(9/30 Pages) TI1

No. de pieza	CDCM1802RGTRG4

Descripción Electrónicos	CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

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Fabricante Electrónico	TI1 [Texas Instruments]

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CDCM1802

LVCMOS

Y1

1 lQ

10 pF

VDD

Y0

|Y0 t Y0|

VOUT(pp)

80%

0 V

20%

tf

tr

VOH

VOL

tPHLO

0.5 x VDD1

tskLVCMOS(o)

IN

Y0

Y1

CDCM1802

www.ti.com

SCAS759B – APRIL 2004 – REVISED NOVEMBER 2015

7 Parameter Measurement Information

A.

Part-to-part skew, tsk(pp), is calculated as the greater of:

M

− The difference between the fastest and the slowest tpd(LH)n across multiple devices

M

− The difference between the fastest and the slowest tpd(HL)n across multiple devices

B.

Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and

the

low-to-high

(tpd(LH))

propagation

delays

when

a

single

switching

input

causes

Y0

to

switch,

tsk(p) = | tpd(HL) − tpd(LH) |. Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew.

Figure 7. Waveforms for Calculation of tsk(o) and tsk(pp)

Figure 8. LVPECL Differential Output Voltage and Rise and Fall Time

Figure 9. LVCMOS Output Loading During Device Test

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Product Folder Links: CDCM1802

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CDCM1802RGTRG4 Datasheet(PDF) 9 Page - Texas Instruments

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