CDCVF2509A

SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010

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Pin Functions

PIN

TYPE

DESCRIPTION

NAME

NO.

Clock input. CLK provides the clock signal to be distributed by the CDCVF2509A clock driver. CLK

is used to provide the reference signal to the integrated PLL that generates the clock output signals.

CLK

24

I

CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit

is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase

lock the feedback signal to its reference signal.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to

FBIN

13

I

FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

nominally zero phase error between CLK and FBIN.

Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4)

1G

11

I

are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the

same frequency as CLK.

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3)

2G

14

I

are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the

same frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as

FBOUT

12

O

CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has

an integrated 25-

Ω series-damping resistor.

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via

1Y (0:4)

3, 4, 5, 8, 9

O

the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control

input. Each output has an integrated 25-

Ω series-damping resistor.

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via

2Y (0:3)

16, 17, 21, 20

O

the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control

input. Each output has an integrated 25-

Ω series-damping resistor.

23

Power

buffered directly to the device outputs.

AGND

1

Ground Analog ground. AGND provides the ground reference for the analog circuitry.

2, 10, 15, 22

Power

Power supply

GND

6, 7, 18, 19

Ground Ground

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

Supply voltage range

–0.5 V to 4.3 V

–0.5 V to 4.6 V

–50 mA

±50 mA

±50 mA

±100 mA

(5)

0.7 W

Storage temperature range

–65°C to 150°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

(3)

The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(4)

This value is limited to 4.6 V maximum.

(5)

The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For

more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book

(SCBD002).

4

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