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CDCVF2509PWR Datasheet(PDF) 4 Page - Texas Instruments |
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CDCVF2509PWR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 16 page NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT AVCC Supply voltage range (2) AVCC < VCC +0.7 V VCC Supply voltage range –0.5 V to 4.3 V VI Input voltage range (3) –0.5 V to 4.6 V VO Voltage range applied to any output in the high or low state(3) (4) –0.5 V to VCC + 0.5 V IIK Input clamp current (VI< 0) –50 mA IOK Output clamp current (VO< 0 or VO > VCC) ±50 mA IO Continuous output current (VO = 0 to VCC) ±50 mA Continuous current through each VCC or GND ±100 mA Maximum power dissipation at TA = 55°C (in still air) (5) 0.7 W Tstg Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) AVCC must not exceed VCC+ 0.7 V (3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) This value is limited to 4.6 V maximum. (5) The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book (SCBD002). DISSIPATION RATINGS TA ≤ 25°C DERATING TA = 70°C TA = 85°C BOARD PACKAGE RqJA POWER RATING FACTORS ABOVE POWER RATING POWER RATING TYPE TA ≤ 25°C PW JEDEC low-K 114.5°C/W 920 mW 8.7 mW/°C 520 mW 390 mW JEDEC 62.1°C/W 1690 mW 16.1 mW/°C 960 mW 720 mW high-K RECOMMENDED OPERATING CONDITIONS (1) MIN MAX UNIT VCC, AVCC Supply voltage 3 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V IOH High-level output current –12 mA IOL Low-level output current 12 mA TA Operating free-air temperature 0 85 °C (1) Unused inputs must be held high or low to prevent them from floating. TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fclk Clock frequency 50 175 MHz Input clock duty cycle 40% 60% Stabilization time(1) 1 ms (1) The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. 4 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 |
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