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CDCVF2510PWRG4 Datasheet(PDF) 4 Page - Texas Instruments

No. de pieza CDCVF2510PWRG4
Descripción Electrónicos  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Fabricante Electrónico  TI1 [Texas Instruments]
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CDCVF2510PWRG4 Datasheet(HTML) 4 Page - Texas Instruments

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RECOMMENDED OPERATING CONDITIONS
(1)
TIMING REQUIREMENTS
ELECTRICAL CHARACTERISTICS
CDCVF2510
SCAS638C – JULY 2001 – REVISED APRIL 2006
DISSIPATION RATING TABLE
DERATING
BOARD
TA≤ 25°C POWER
TA = 70°C POWER
TA = 85°C POWER
PACKAGE
RΘJA
FACTOR(2) ABOVE
TYPE(1)
RATING
RATING
RATING
TA = 25°C
JEDEC low-K
114.5°C/W
920 mW
8.7 mW/°C
520 mW
390 mW
PW
JEDEC high-K
62.1°C/W
1690 mW
16.1 mW/°C
960 mW
720 mW
(1)
JEDEC high-K board has better thermal performance due to multiple internal copper planes.
(2)
This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA).
MIN
MAX
UNIT
VCC, AVCC
Supply voltage
3
3.6
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
IOH
High-level output current
-12
mA
IOL
Low-level output current
12
mA
TA
Operating free-air temperature
0
85
°C
(1)
Unused inputs must be held high or low to prevent them from floating.
over recommended ranges of supply voltage and operating free-air temperature
MIN
MAX
UNIT
fclk
Clock frequency(1)
50
175
MHz
Input clock duty cycle
40%
60%
Stabilization time(2)
1
ms
(1)
To avoid any self oscillation of the PLL, a continous clock signal has to be present at the clock input.
(2)
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the Switching Characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC, AVCC
MIN
TYP(1)
MAX
UNIT
VIK
Input clamp voltage
II = -18 mA
3 V
-1.2
V
IOH = -100 µA
MIN to MAX
VCC-0.2
VOH
High-level output voltage
IOH = -12 mA
3 V
2.1
V
IOH = -6 mA
3 V
2.4
IOL = 100 µA
MIN to MAX
0.2
VOL
Low-level output voltage
IOL = 12 mA
3 V
0.8
V
IOL = 6 mA
3 V
0.55
VO = 1 V
3 V
-28
IOH
High-level output current
VO = 1.65 V
3.3 V
-36
mA
VO = 3.135 V
3.6 V
-8
VO = 1.95 V
3 V
30
IOL
Low-level output current
VO = 1.65 V
3.3 V
40
mA
VO = 0.4 V
3.6 V
10
II
Input current
VI = VCC or GND
3.6 V
±5
µA
(1)
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
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