Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

AD9289 Datasheet(PDF) 11 Page - Analog Devices

No. de pieza AD9289
Descripción Electrónicos  Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9289 Datasheet(HTML) 11 Page - Analog Devices

Back Button AD9289 Datasheet HTML 7Page - Analog Devices AD9289 Datasheet HTML 8Page - Analog Devices AD9289 Datasheet HTML 9Page - Analog Devices AD9289 Datasheet HTML 10Page - Analog Devices AD9289 Datasheet HTML 11Page - Analog Devices AD9289 Datasheet HTML 12Page - Analog Devices AD9289 Datasheet HTML 13Page - Analog Devices AD9289 Datasheet HTML 14Page - Analog Devices AD9289 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 16 page
background image
Preliminary Technical Data
AD9289
Rev. PrJ | Page 11 of 16
6/25/2004
X
Selected Mode
SENSE Voltage
Internal Switch Position
Resulting VREF (V)
Resulting Differential
Span (V p-p)
External Reference
AVDD
N/A
N/A
2 × External Reference
Internal
VREF
SENSE
0.5
1.0
Programmable
0.2 V to VREF
SENSE
0.5 × (1 + R2/R1)
2 × VREF
Internal
AGND to 0.2 V
Internal Divider
1.0
2.0
Table 1 Reference Settings
Digital Outputs
The AD9289’s differentialoutputs conform to the ANSI-644 LVDS
standard. To set the LVDS bias current, place a resistor (RSET is
nominally equal to 3.8 k
Ω) to ground at the LVDSBIAS pin. The
RSET resistor current (~ 1.2/RSET) is ratioed on-chip setting the
output current at each output equal to a nominal 3.5 mA. A 100
differential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
The AD9289’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments. Single
point-to-point net topologies are recommended with a 100
termination resistor as close to the receiver as possible. It is
recommended to keep the trace length no longer than 3 inches and
to keep differential output trace lengths as equal as possible.
The format of the output data can be selected as offset binary or
twos complement. Pin S1 is used to set the format.
S1 Mode
Data Format
AVDD
Twos Complement
AGND
Offset Binary
Table 6: S1 Configuration
Timing
Data from each A/D is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 8-bits
times the sample clock rate, with a maximum of 520 MHz (8-bits x
65 MSPS = 520 MHz). The lowest typical conversion rate is 20
MSPS.
Two output clocks are provided to assist in capturing data from the
AD9289. The data clock out (DCO) is used to clock the output
data and is equal to four times the sampling clock (CLK) rate.
Data is clocked out of the AD9289 on the rising and falling edges
of DCO. The FCO clock is used to signal the start of a new output
byte and is equal to the sampling clock rate. See the Timing
Diagram for more information.
PLL LOCK Output
The AD9289 contains an internal PLL that is used to generate the
data clock out (DCO). When the PLL is locked, the LOCK/ signal
will be low, indicating valid data on the outputs.
If for any reason the PLL loses lock, the LOCK/ signal will go
high as soon as the lock circuitry detects an unlocked condition.
While the PLL is unlocked, the data outputs and DCO will remain
in the last known state. If the LOCK/ signal goes high in the
middle of a byte, no data or DCO signals will be available for the
rest of the byte. It will take at least 1
µs to regain lock if lock is
lost.
Once the PLL regains lock, the DCO will start. The first valid data
byte will be indicated by the FCO signal. See the Timing Diagram
for more information.
CML Pin
A common mode level output is available at F3. This output self-
biases to AVDD/2. This is a relatively high impedance output (two
5K resistors in series between AVDD and ground) with an output
impedance of 2.5K which may need to be considered when using
as a reference.
Overange
The AD9289 has an Overange output available that indicates when
the ADC is driven out of range. OR+ is driven high in overrange
condition, with the digital outputs are clamped to all zeroes or all
ones.Pin Function Descriptions


Número de pieza similar - AD9289

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Analog Devices
AD9289 AD-AD9289 Datasheet
917Kb / 33P
   Serial LVDS 3 V A/D Converter
AD9289-65EB AD-AD9289-65EB Datasheet
917Kb / 33P
   Serial LVDS 3 V A/D Converter
AD9289-65EB1 AD-AD9289-65EB1 Datasheet
902Kb / 28P
   High Speed ADC USB FIFO Evaluation Kit
REV. 0
AD9289BBC AD-AD9289BBC Datasheet
917Kb / 33P
   Serial LVDS 3 V A/D Converter
AD9289 AD-AD9289_15 Datasheet
1Mb / 32P
   Quad 8-Bit, 65 MSPS, Serial LVDS 3 V A/D Converter
REV. 0
More results

Descripción similar - AD9289

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Analog Devices
AD9229 AD-AD9229 Datasheet
471Kb / 15P
   Quad 12-Bit, 50/65 MSPS Serial LVDS 3V A/D Converter
Rev. PrF 10/06/2003
AD9289 AD-AD9289_15 Datasheet
1Mb / 32P
   Quad 8-Bit, 65 MSPS, Serial LVDS 3 V A/D Converter
REV. 0
AD9219 AD-AD9219 Datasheet
1Mb / 52P
   Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
REV. 0
AD9229-65EBZ AD-AD9229-65EBZ Datasheet
789Kb / 40P
   Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter
REV. B
AD9228 AD-AD9228_07 Datasheet
1Mb / 52P
   Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
Rev. B
AD9228 AD-AD9228 Datasheet
1Mb / 52P
   Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
REV. 0
AD9229 AD-AD9229_15 Datasheet
789Kb / 40P
   Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter
REV. B
AD9228 AD-AD9228_15 Datasheet
2Mb / 56P
   Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
Rev. E
logo
Texas Instruments
ADC10065 TI1-ADC10065_14 Datasheet
1Mb / 27P
[Old version datasheet]   10-Bit 65 MSPS 3V A/D Converter
ADC10065 TI1-ADC10065_15 Datasheet
1Mb / 26P
[Old version datasheet]   10-Bit 65 MSPS 3V A/D Converter
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com