ADV7125JST330 datasheet(4/12 Pages) AD

No. de pieza	ADV7125JST330

Descripción Electrónicos	CMOS, 330 MHz Triple 8-Bit High Speed Video DAC

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Fabricante Electrónico	AD [Analog Devices]

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REV. 0

–4–

ADV7125

5 V TIMING SPECIFICATIONS

1 (VAA = 5 V ± 5%

2, V

REF = 1.235 V, RSET = 560

, CL = 10 pF. All specifications TMIN to TMAX

3,

unless otherwise noted, TJ MAX = 110 C.)

Parameter

Min

Typ

Max

Unit

Condition

ANALOG OUTPUTS

Analog Output Delay, t6

5.5

ns

Analog Output Rise/Fall Time, t7

4

1.0

ns

Analog Output Transition Time, t8

5

15

ns

Analog Output Skew, t9

6

12ns

CLOCK CONTROL

fCLK

7

0.5

50

MHz

50 MHz Grade

fCLK

7

0.5

140

MHz

140 MHz Grade

fCLK

7

0.5

240

MHz

240 MHz Grade

Data and Control Setup, t1

6

0.5

ns

Data and Control Hold, t2

6

1.5

ns

Clock Period, t3

4.17

ns

Clock Pulsewidth High, t4

6

1.875

ns

fCLK_MAX = 240 MHz

Clock Pulsewidth Low, t5

6

1.875

ns

fCLK_MAX = 240 MHz

Clock Pulsewidth High, t4

6

2.85

ns

fCLK_MAX = 140 MHz

Clock Pulsewidth Low, t5

6

2.85

ns

fCLK_MAX = 140 MHz

Clock Pulsewidth High, t4

8.0

ns

fCLK_MAX = 50 MHz

Clock Pulsewidth Low, t5

8.0

ns

fCLK_MAX = 50 MHz

Pipeline Delay, tPD

6

1.0

Clock Cycles

PSAVE Up Time, t10

6

210

ns

NOTES

1Timing specifications are measured with input levels of 3.0 V (V

IH) and 0 V (VIL) for both 5 V and 3.3 V supplies.

2These maximum and minimum specifications are guaranteed over this range.

3Temperature range T

MIN to TMAX: –40

°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.

4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.

5Measured from 50% point of full-scale transition to 2% of final value.

6Guaranteed by characterization.

7f

CLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.

Specifications subject to change without notice.

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