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SN74HC132N Datasheet(PDF) 4 Page - Texas Instruments

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No. de pieza SN74HC132N
Descripción Electrónicos  Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
www.ti.com
Product Folder Links: SN54HC132 SN74HC132
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Copyright © 1982–2016, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
7
V
IIK
Input clamp current(2)
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.3 Recommended Operating Conditions
See
(1)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Operating free-air temperature
SN54HC132
–55
125
°C
SN74HC132
–40
85
(1)
For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal
Metrics.
(2)
The package thermal impedance is calculated in accordance with JESD 51-7.
6.4 Thermal Information
THERMAL METRIC(1)
SN74HC132
UNIT
D
(SOIC)
DB
(SSOP)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance(2)
84.3
99.1
50.9
84.3
113.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.8
51.3
38.2
42.2
42.8
°C/W
RθJB
Junction-to-board thermal resistance
38.5
46.3
30.8
43.0
54.8
°C/W
ψJT
Junction-to-top characterization parameter
13.9
17.7
23.1
13.5
4.0
°C/W
ψJB
Junction-to-board characterization parameter
38.2
45.8
30.7
42.7
54.3
°C/W


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