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LM26480-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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LM26480-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 39 page 6 LM26480-Q1 SNVSA58A – JANUARY 2015 – REVISED JUNE 2016 www.ti.com Product Folder Links: LM26480-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the potential at the GND pin. (3) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm. (4) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range. (5) Specified by design. Not production tested. 7.5 General Electrical Characteristics Unless otherwise noted, VIN = 3.6 V. Values and limits apply for TJ = 25°C. (1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ VINLDO12 shutdown current VIN = 3.6 V 0.5 µA VPOR Power-on reset threshold VDD falling edge (4) 1.9 V TSD Thermal shutdown threshold See(5) 160 °C TSDH Thermal shutdown hysteresis See(5) 20 UVLO Undervoltage lockout Rising 2.9 V Failing 2.7 (1) All voltages are with respect to the potential at the GND pin. (2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the most likely norm. (3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. (4) The device maintains a stable, regulated output voltage without a load. (5) Pins 24, 19 can operate from VIN min of 1.74 V to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. (6) VIN minimum for line regulation values is 1.8 V. (7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. 7.6 Low Dropout Regulators, LDO1 and LDO2 Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, and values and limits apply for TJ = 25°C, unless otherwise specified. (1) (2) (3) (4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Operational voltage range VINLDO1 and VINLDO2 PMOS pins(5) TJ = −40°C to 125°C 1.74 5.5 V VFB FB voltage accuracy TJ = −40°C to 125°C –3% 3% ΔVOUT Line regulation VIN = (VOUT + 0.3 V) to 5 V (6) Load current = 1 mA TJ = −40°C to 125°C 0.15 %/V Load regulation VIN = 3.6 V, TJ = −40°C to 125°C Load current = 1 mA to IMAX 0.011 %/mA ISC Short circuit current limit LDO1-2, VOUT = 0 V 500 mA VIN – VOUT Dropout voltage Load current = 50 mA(7) 25 mV Load current = 50 mA(7) TJ = −40°C to 125°C 200 PSRR Power supply ripple rejection F = 10 kHz, load current = IMAX 45 dB eN Supply output noise 10 Hz < F < 100 kHz 150 µVRMS IQ Quiescent current on IOUT = 0 mA 40 µA IOUT = 0 mA, −40°C ≤ TJ ≤ 125°C 150 Quiescent current on IOUT = 300 mA 60 IOUT = 300 mA, −40°C ≤ TJ ≤ 125°C 200 Quiescent current off EN is de-asserted 0.03 1 µA TON Turnon time Start-up from shutdown 300 µsec |
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