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SN74AHCT240PWLE Datasheet(PDF) 8 Page - Texas Instruments |
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SN74AHCT240PWLE Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page 1Y1 1OE 1A1 1Y2 1A2 1Y3 1A3 1Y4 1A4 2Y1 2OE 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4 Copyright © 2016, Texas Instruments Incorporated 8 SN54AHCT240, SN74AHCT240 SCLS252M – OCTOBER 1995 – REVISED APRIL 2016 www.ti.com Product Folder Links: SN54AHCT240 SN74AHCT240 Submit Documentation Feedback Copyright © 1995–2016, Texas Instruments Incorporated 9 Detailed Description 9.1 Overview The SN74AHCT240 devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram 9.3 Feature Description • VCC is optimized at 5 V • Allows up-voltage translation from 3.3 V to 5 V – Inputs accept VIH levels of 2 V • Slow edge rates minimize output ringing • Inputs are TTL-voltage compatible 9.4 Device Functional Modes Table 1. Function Table (Each 4-bit Buffer/Driver) INPUTS OUTPUT Y OE A L H H L L L H X Z |
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