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SN74ALVCH16524DLR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74ALVCH16524DLR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 12 page www.ti.com FEATURES DESCRIPTION/ORDERING INFORMATION DGG OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND OEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA CLKENBA GND SEL B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLK GND SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080E – JULY 1996 – REVISED OCTOBER 2004 • Member of the Texas Instruments Widebus™ Family • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode • Operates From 1.65 V to 3.6 V • Max tpd of 3.2 ns at 3.3 V • ±24-mA Output Drive at 3.3 V • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74ALVCH16524DL SSOP - DL ALVCH16524 -40 to 85 °C Tape and reel SN74ALVCH16524DLR TSSOP - DGG Tape and reel SN74ALVCH16524DGGR ALVCH16524 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1996–2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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