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LM4970 Datasheet(PDF) 10 Page - Texas Instruments |
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LM4970 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 19 page LM4970 SNVS312D – JANUARY 2005 – REVISED MAY 2013 www.ti.com Table 6. Current Select Register (continued) Default Data Bit Bit Name Condition Function Value Programs the current drive of the LED3 driver. Current drive for LED3 is set 0 as follows: CS4 ILED3_0 0 1 ILED3<1:0> Current Drive Setting 00 0.66X 0 01 1X CS5 ILED3_1 1 10 1.33X 1 11 2X Table 7. Gain Select Register Default Data Bit Bit Name Condition Function Value 0 Programs the gain response of the midband audio synchronized filter which GSO MGAIN0 0 drives the LED2 PWM color LED driver for the midband audio frequencies. 1 Gain is set as follows: 0 Midband Filter Gain GS1 MGAIN1 1 MGAIN<2:0> 1 0 000 minimum 001 low GS2 MGAIN2 0 010 medium 1 011 high 100 maximum Programs the audio gain of the input summing amplifier. Gain is set as 0 follows: GS3 SGAIN0 0 1 SGAIN<2:0> Input Signal Gain 0 000 –11dB GS4 SGAIN1 1 1 001 –6.5dB 010 0dB 0 011 3.5dB GS5 SGAIN2 0 100 6dB 1 101 10dB 110 12dB I 2C COMPATIBLE INTERFACE The LM4970 uses a serial bus which conforms to the I2C protocol to control the chip’s functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector) with a pullup resistor (typically 10k Ω). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4970. The I2C address for the LM4970 is determined using the ADR pin. The LM4970’s two possible I2C chip addresses are of the form 111101X10 (binary), where X1 = 0, if ADR is logic low; and X1 = 1, if ADR is logic high. If the I2C interface is used to address a number of chips in a system, the LM4970’s chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 14. The data is latched in on the rising edge of the clock. The bus format diagram is broken up into six major sections: The “start” signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the clock level is high. 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4970 |
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