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TDC7201ZAXT Datasheet(PDF) 4 Page - Texas Instruments |
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TDC7201ZAXT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 50 page 4 TDC7201 SNAS686 – MAY 2016 www.ti.com Product Folder Links: TDC7201 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (3) All voltages are with respect to ground, unless otherwise specified. (4) Pins VDD1 and VDD2 must be tied together at the board level and supplied from the same source. (5) When the terminal input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > VDD), the current at that pin must not exceed 5 mA (source or sink), and the voltage (VI) at the pin must not exceed 3.9 V. 6 Specifications 6.1 Absolute Maximum Ratings at TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted). (1) (2) (3) (4) (5) MIN MAX UNIT VDD Supply voltage –0.3 3.9 V VI Voltage on VREG1, VREG2 pins –0.3 1.65 V Terminal input voltage on any other pin –0.3 VDD + 0.3 VDIFF_IN |Voltage differential| between any two input terminals 3.9 V VIN_GND_VDD |Voltage differential| between any input terminal and GND or VDD 3.9 V II Input current at any pin –5 5 mA TA Ambient temperature –40 125 °C Tstg Storage temperature –55 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250 (1) Specified by design. (2) Applies to both pairs of START1, STOP1 and START2, STOP2 pins. (3) Minimum time between 2 stop signals applies to 2 stop signals on the same TDC. 6.3 Recommended Operating Conditions At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted). MIN NOM MAX UNIT VDD Supply voltage 2 3.6 V VI Terminal voltage 0 VDD V VIH Voltage input high 0.7 × VDD 3.6 V VIL Voltage input low 0 0.3 × VDD V FCALIB_CLK Frequency (reference or calibration clock) 1 (1) 8 16 MHz tCLOCK Time period (reference or calibration clock) 62.5 125 1000 ns DUTYCLOCK Input clock duty cycle 50% TIMING REQUIREMENTS: Measurement Mode 1 (1)(2)(3) T1Min_STARTSTOP Minimum time between start and stop signal 12 ns T1Max_STARTSTOP Maximum time between start and stop signal 2000 ns T1Min_STOPSTOP Minimum time between 2 stop signals 67 ns T1Max_LASTSTOP Maximum time between start and last stop signal 2000 ns TIMING REQUIREMENTS: Measurement Mode 2(1)(2)(3) T2Min_STARTSTOP Minimum time between start and stop signal 2 × tCLOCK s T2Max_STARTSTOP Maximum time between start and stop signal (216-2) × tCLOCK s T2Min_STOPSTOP Minimum time between 2 stop signals 2 × tCLOCK s T2Max_LASTSTOP Maximum time between start and last stop signal (216-2) × tCLOCK s |
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