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CAP1206-2-SL-TR Datasheet(PDF) 7 Page - Microchip Technology |
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CAP1206-2-SL-TR Datasheet(HTML) 7 Page - Microchip Technology |
7 / 63 page 2013-2015 Microchip Technology Inc. DS00001567B-page 7 CAP1206 2.0 ELECTRICAL SPECIFICATIONS Note 2-1 Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 2-2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V5VT_PIN and VDD must never exceed 3.6V. Note 2-3 The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 2x3 matrix of 0.3mm (12mil) vias at 0.9mm pitch connected to the ground plane with a 1.6 x 2.3mm thermal landing. Note 2-4 Junction to Ambient ( JA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the JA will be higher. TABLE 2-1: ABSOLUTE MAXIMUM RATINGS Voltage on VDD pin -0.3 to 6.5 V Voltage on CS pins to GND -0.3 to 4.0 V Voltage on 5V tolerant pins (V5VT_PIN) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_PIN - VDD|) (see Note 2-2)0 to 3.6 V Input current to any pin except VDD +10 mA Output short circuit current Continuous N/A Package Power Dissipation up to TA = 85°C for 10-pin DFN (see Note 2-3) 0.5 W Junction to Ambient ( JA) (see Note 2-4)78 °C/W Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 8000 V |
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