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TLC2552IDGK Datasheet(PDF) 3 Page - Texas Instruments |
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TLC2552IDGK Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS276D – MARCH 2000 – REVISED MAY 2003 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TLC2551 TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time. CS can be used as the FS pin when a dedicated DSP serial port is used. FS 7 I DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SCLK 5 I Output serial clock. This terminal receives the serial SCLK from the host processor. SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge or FS rising edge, whichever occurs first. The output format is MSB first. When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after CS falling edge and output data is valid on the first falling edge of SCLK. When CS and FS are both used (FS = 0 at the falling edge of CS), the MSB is presented to the SDO pin after the falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after rising FS. Output data is valid on the first falling edge of SCLK. (This is typically used with an active FS from a DSP.) VDD 6 I Positive supply voltage VREF 2 I External reference input TLC2552/55 TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AIN0 /AIN(+) 4 I Analog input channel 0 for TLC2552—Positive input for TLC2555 AIN1/AIN (–) 5 I Analog input channel 1 for TLC2552—Inverted input for TLC2555 CS 1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can be connected to the FS output from a DSP on a dedicated serial port. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SCLK 7 I Output serial clock. This terminal receives the serial SCLK from the host processor. SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge. VDD 6 I Positive supply voltage VREF 2 I External reference input detailed description The TLC2551, TLC2552, and TLC2555 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. |
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