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TPD4E001DRSR Datasheet(PDF) 11 Page - Texas Instruments |
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TPD4E001DRSR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 28 page VCC GND IO3 IO4 = VIA to GND IO1 IO2 GND 0.1µF 11 TPD4E001 www.ti.com SLLS682L – JULY 2006 – REVISED MAY 2016 Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 9 Power Supply Recommendations This device is a passive ESD protection device so there is no need to power it. Take care to make sure that the maximum voltage specifications for each pin are not violated. 10 Layout 10.1 Layout Guidelines • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. • Route the protected traces as straight as possible. • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example The following is a layout example for protecting two interface ports with the TPD4E001. One example would be two USB 2.0 ports, as was discussed in the Application and Implementation section. For the USB 2.0 example, IO1 and IO2 would be D+ and D-, respectively, of USB port 1. IO3 and IO4 would be D- and D+, respectively, of USB port 2. Figure 6. Routing With DRL Package |
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