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STK11C68-5K35M Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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STK11C68-5K35M Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 10 page STK11C68-M 4-37 #1 Alt. MIN MAX MIN MAX MIN MAX (VCC = 5.0V ± 10%) STORE/RECALL CYCLE 22 tAVAV tRC STORE/RECALL Initiation Cycle Time 35 45 55 ns 23 tELQZ p Chip Enable to Output Inactive 75 75 85 ns 24 tELQXS tSTORE q STORE Cycle Time 10 10 10 ms 25 t ELQXR t RECALL r RECALL Cycle Time 20 20 20 µs 26 t AVELN s t AE Address Set-up to Chip Enable 0 0 0 ns 27 tELEHN s,t tEP Chip Enable Pulse Width 25 35 45 ns 28 tEHAXN s tEA Chip Disable to Address Change 0 0 0 ns SYMBOLS STK11C68-35M STK11C68-45M STK11C68-55M NO. PARAMETER UNITS Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note q: Note that STORE cycles (but not RECALLs) are aborted by VCC < 4.0V (STORE inhibit). Note r: A RECALL cycle is initiated automatically at power up when VCC exceeds 4.0V. tRECALL is measured from the point at which VCC exceeds 4.5V. Note s: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence. Note t: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. Note u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK11C68-M performs a STORE or RECALL. Note v: E must be used to clock in the address sequence for the Software STORE and RECALL cycles. STORE/RECALL CYCLE u,v ADDRESS E DATA OUT DATA VALID ADDRESS #6 ADDRESS #1 DATA VALID HIGH IMPEDANCE 22 tAVAV 22 tAVAV 26 tAVELN 27 tELEHN 28 tEHAXN 24 tSTORE 25 tRECALL 23 tELQZ |
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