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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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DM6380L Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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DM6380L Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
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10 / 40 page  DM336P V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set 10 Final Version: DM336P-DS-F02 August 15, 2000 c. Interrupt Identification Register (IIR): Address 2 Reset State 01h, Read only bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FIFO Enable 000 D3: INTD2 D2: INTD1 D1: INTD0 D0: int Pending In order to provide minimum software overhead during data transfers, the virtual UART prioritizes interrupts into four levels as followed: Receiver Line Status (priority 1), Receiver Data Available (priority 2), Character Timeout Indication (priority 2, FIFO mode only), Transmitter Holding Register Empty (priority 3 ), and Modem Status (priority 4). The IIR register gives prioritized information as to the status of interrupt conditions. When accessed, the IIR indicates the highest priority interrupt that is pending, as indicated by bits INTD(2-0). Bit 0: This bit can be used in either a prioritized interrupt or polled environment to indicate whether an interrupt is pending. When this bit is a logic 0, an interrupt is pending, and the IIR contents may be used as a pointer to the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is pending, and polling (if used) continues. Bit 1-2: These two bits of the IIR are used to identify the highest priority interrupt pending, as indicated in the table below. Bit 3: In character mode, this bit is 0. In FIFO mode, this bit is set, along with bit 2, when a timeout interrupt is pending. Bit 4-6: Not used Bit 7: This bit is set when FCR0 = 1. D3 D2 D1 D0 Priority Level Interrupt Type Condition Reset 00 0 1 - - - - 0 1 1 0 Highest Receiver Line Status Overrun Error, Parity Error, Framing Error or Break Interrupt Reads the Line Status Register 0 1 0 0 Second Receiver Data Available Receiver Data Available or Trigger Level Reached Reads the Receiver Buffer Register or the FIFO Drops Below The Threshold Value 1 1 0 0 Second Character Timeout Indication No characters have been read from or written to the Rx FIFO during programming time interval, and the Rx FIFO is not empty Reads The Receiver Buffer Register 0 0 1 0 Third Transmitter Holding Register Empty Transmitter Holding Register Empty Reads the IIR Register or (if source of interrupt) Writes To The Transmitter Holding Register 0 0 0 0 Fourth Modem Status Clear to Send, Data Set Ready, Ring Indicator or Data Carrier Detected Reads the Modem Status Register |
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Descripción similar - DM6380L |
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