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TSB41LV06APZP Datasheet(PDF) 1 Page - Texas Instruments

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No. de pieza TSB41LV06APZP
Descripción Electrónicos  IEEE 1394b SIX-PORT CABLE TRANSCEIVER/ARBITER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TSB41LV06APZP Datasheet(HTML) 1 Page - Texas Instruments

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TSB41LV06A
IEEE 1394a SIXPORT CABLE TRANSCEIVER/ARBITER
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Fully Supports Provisions of IEEE 1394−
1995 Standard for High Performance Serial
Busand the P1394a Supplement
D Fully Interoperable With FireWire and
i.LINK
 Implementation of IEEE Std 1394
D Fully Compliant With OpenHCI
Requirements
D Provides Six P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s)
D Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume
D Extended Resume Signaling for
Compatibility With Legacy DV Devices
D Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and Inactive
Ports Powered-Down
D Ultralow-Power Sleep Mode
D Node Power Class Information Signaling
for System Power Management
D Cable Power Presence Monitoring
D Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
D Register Bits Give Software Control of
Contender Bit, Power Class bits, Link
Active Control Bit and P1394a Features
D Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
D Interface to Link Layer Controller Supports
Low Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation
D Interoperable With Link-Layer Controllers
Using 3.3 V and 5 V Supplies
D Interoperable With Other Physical Layers
(PHYs) Using 3.3 V and 5 V Supplies
D Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
D Incoming Data Resynchronized to Local
Clock
D Logic Performs System Initialization and
Arbitration Functions
D Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
D Separate Cable Bias (TPBIAS) for Each Port
D Single 3.3-V Supply Operation
D Low Cost High Performance 100-Pin TQFP
(PZP) Thermally Enhanced Package
D Direct Drop-In Upgrade for TSB41LV06PZP
description
The TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
Copyright
 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computer, Incorporated.


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