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SM65MLVD080DGGR Datasheet(PDF) 6 Page - Texas Instruments |
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SM65MLVD080DGGR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 24 page SN65MLVD080 SN65MLVD082 SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003 www.ti.com 6 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 2 4 6 ns tpHL Propagation delay time, high-to-low-level output 2 4 6 ns tr Output signal rise time 1 2.3 ns tf Output signal fall time CL = 15 pF, See Figure 10 1 2.3 ns tsk(o) Output skew CL = 15 pF, See Figure 10 350 ps tsk(p) Pulse skew (|tpHL − tpLH|) 50 350 ps tsk(pp) Part-to-part skew(2) 1 ns tjit(per) Period jitter, rms (1 standard deviation) (3) 100 MHz clock input(4) 7 ps tjit(c−c) Cycle-to-cycle jitter, rms 100 MHz clock input(4) 110 ps tjit(det) Deterministic jitter Type 1 550 ps tjit(det) Deterministic jitter Type 2 200 Mbps 215−1 PRBS input(5) 480 ps tjit(pp) Peak-to-peak jitter(3)(6) Type 1 200 Mbps 215−1 PRBS input(5) 720 ps tjit(pp) Peak-to-peak jitter(3)(6) Type 2 660 ps tpZH Enable time, high-impedance-to-high-level output 30 ns tpZL Enable time, high-impedance-to-low-level output CL = 15 pF, See Figure 11 30 ns tpHZ Disable time, high-level-to-high-impedance output CL = 15 pF, See Figure 11 18 ns tpLZ Disable time, low-level-to-high-impedance output 28 ns (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) VID = 200 mVpp (’080), VID = 400 mVpp (’082), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. (5) VID = 200 mVpp (’080), VID = 400 mVpp (’082), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. (6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). |
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