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TMP32C6411AGLZ Datasheet(PDF) 4 Page - Texas Instruments |
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TMP32C6411AGLZ Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 119 page  TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 64 Power-supply decoupling section: Updated/changed the “In order to properly decouple the supply planes from system noise, place as many capacitors ...” paragraph Added two subsequent paragraphs 65 IEEE 1149.1 JTAG compatibility statement section: Updated/added paragraphs for clarity 66 Reset section: Added new section 75 Asynchronous Memory Timing section: Timing Requirements for Asynchronous Memory Cycles table: Added/split silicon revisions “Rev 1.1” and “Rev 2.0” for the MIN value of parameter #7 “th(EKO1H-ARDY), Hold time, ARDY valid after ECLKOUTx high” Added the MIN value of “1.3” ns for “Rev 2.0” 89 HOLD/HOLDA Timing section: Timing Requirements for the HOLD/HOLDA Cycles table: Changed parameter NO. 3 from “toh(HOLDAL-HOLDL)” to “th(HOLDAL-HOLDL)” 91 Reset Timing section: Timing Requirements for Reset table: Changed the MIN value of parameter No. 16, tsu(boot) from “4P” to “4E or 4C” ns Added associated footnote to identify “E” and “C” Added parameter NO. 18, “td(PCLK−RSTH) Delay time, PCLK active to RESET high” with a MIN value of “32N” ns Changed parameter NO. 18 description from “td(PCLK−RSTH) Delay time, PCLK active to RESET high” to “tsu(PCLK-RSTH), Setup time, PCLK active before RESET high” Added associated footnote to identify “N” and restraints Switching Characteristics Over Recommended Operating Conditions During Reset table: Moved parameter NO. 18, “td(PCLK−RSTH) Delay time, PCLK active to RESET high” to the Timing Requirements for Reset table Updated footnote symbols 94 Host-Port Interface (HPI) Timing section: Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles table: Added “mode, 2nd half-word” to parameter NO. 16 “td(HSTBL-HDV), Delay time, HSTROBE low to HD valid (HPI16 only)” 103−104 Multichannel Buffered Serial Port (McBSP) Timing section: Switching Characteristics Over Recommended Operating Conditions for McBSP table: Changed the MIN value of parameter #12 “tdis(CKXH-DXHZ), Disable time, DX high impedance following last data bit from CLKX high, CLKX ext” from “−2.1” to “2.0” ns Changed the MIN value of parameter #13 “td(CKXH-DXV), Delay time, CLKX high to DX valid, CLKX ext” from “−2.1 + D1” to “2.0 + D1” ns Changed the MIN value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX int” from “−2.3” to “−2.3 + D1h” ns Changed the MAX value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX int” from “5.6” to “5.6 + D2h” ns Changed the MIN value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX ext” from “1.9” to “1.9 + D1h” ns Changed the MAX value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX ext” from “9” to “9 + D2h” ns Added associated footnote Figure 51, McBSP Timing: Added footnote for clarity |
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