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CDC304 Datasheet(PDF) 3 Page - Texas Instruments |
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CDC304 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 6 page CDC304 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS325A – JULY 1990 – REVISED NOVEMBER 1995 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VCC = 4.5 V, II = – 18 mA – 1.2 V VOH VCC = 4.5 V, IOH = – 2 mA VCC –2 V VOH VCC = 4.5 V, IOH = – 24 mA 2 2.8 V VOL VCC = 4.5 V, IOL = 48 mA 0.3 0.5 V II VCC = 5.5 V, VI = 7 V 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 µA IIL VCC = 5.5 V, VI = 0.4 V – 0.5 mA IO‡ VCC = 5.5 V, VO = 2.25 V –50 – 150 mA ICC VCC = 5.5 V, See Note 2 45 75 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 2: ICC is measured with CLK and PRE grounded, then with CLK and CLR grounded. timing requirements MIN MAX UNIT fclock Clock frequency 0 80 MHz CLR or PRE low 5 tw Pulse duration CLK high 4 ns CLK low 6 tsu Setup time before CLK ↑ CLR or PRE inactive 6 ns switching characteristics over recommended operating free-air temperature range (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP† MAX UNIT fmax§ 80 MHz tPLH CLK Q RL = 500 Ω CL =50 pF 2 6 9 ns tPHL CLK Q RL = 500 Ω, CL = 50 pF 2 6 9 ns tPLH PRE or CLR Q RL = 500 Ω CL =50 pF 3 7 12 ns tPHL PRE or CLR Q RL = 500 Ω, CL = 50 pF 3 7 12 ns tsk(o) CLK Q RL = 500 Ω, See Figure 2 CL = 10 pF to 30 pF, 1 ns t k( ) CLK Q1, Q8 RL = 500 Ω CL =10 pFto30 pF 1 ns tsk(p) CLK Q2 – Q7 RL = 500 Ω, CL = 10 pF to 30 pF 1.5 ns tr 4.5 ns tf 3.5 ns † All typical values are at VCC = 5 V, TA = 25°C. § fmax minimum values are at CL = 0 to 30 pF. |
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