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MC10EP35 Datasheet(PDF) 1 Page - ON Semiconductor

No. de pieza MC10EP35
Descripción Electrónicos  ECL JK Flip?륡lop
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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MC10EP35 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 7
1
Publication Order Number:
MC10EP35/D
MC10EP35, MC100EP35
3.3V / 5V ECL JK Flip‐Flop
Description
The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip-flop. The J/K data enters the master portion of the
flip-flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
Features
410 ps Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at VEE
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
H
= MC10
A = Assembly Location
K
= MC100 L
= Wafer Lot
5R = MC10
Y = Year
3M = MC100 W = Work Week
M = Date Code
G
= Pb-Free Package
ALYWG
G
HP35
ALYWG
G
KP35
MARKING DIAGRAMS*
1
8
1
8
www.onsemi.com
HEP35
ALYW
G
1
8
KEP35
ALYW
G
1
8
14
14
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information on page 7 of
this data sheet.
ORDERING INFORMATION
SOIC−8NB
D SUFFIX
CASE
751−07
TSSOP−8
DT SUFFIX
CASE
948R−02
1
8
1
8
DFN−8
MN SUFFIX
CASE 506AA


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