TSB12LV26-EP_14 datasheet(3/85 Pages) TI1

No. de pieza	TSB12LV26-EP

Descripción Electrónicos	OHCI-Lynx PCI-Based IEEE 1394 Host controller

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Fabricante Electrónico	TI1 [Texas Instruments]

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4.6

CSR Control Register

4−7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7

Configuration ROM Header Register

4−8

. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8

Bus Identification Register

4−8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9

Bus Options Register

4−9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10

GUID High Register

4−10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11

GUID Low Register

4−10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12

Configuration ROM Mapping Register

4−11

. . . . . . . . . . . . . . . . . . . . . . . . . .

4.13

Posted Write Address Low Register

4−11

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14

Posted Write Address High Register

4−12

. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15

Vendor ID Register

4−12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16

Host Controller Control Register

4−13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17

Self-ID Buffer Pointer Register

4−14

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18

Self-ID Count Register

4−15

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19

Isochronous Receive Channel Mask High Register

4−16

. . . . . . . . . . . . . .

4.20

Isochronous Receive Channel Mask Low Register

4−17

. . . . . . . . . . . . . . .

4.21

Interrupt Event Register

4−18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22

Interrupt Mask Register

4−20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23

Isochronous Transmit Interrupt Event Register

4−22

. . . . . . . . . . . . . . . . . .

4.24

Isochronous Transmit Interrupt Mask Register

4−23

. . . . . . . . . . . . . . . . . . .

4.25

Isochronous Receive Interrupt Event Register

4−24

. . . . . . . . . . . . . . . . . . .

4.26

Isochronous Receive Interrupt Mask Register

4−25

. . . . . . . . . . . . . . . . . . .

4.27

Fairness Control Register

4−25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28

Link Control Register

4−26

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.29

Node Identification Register

4−27

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.30

PHY Layer Control Register

4−28

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.31

Isochronous Cycle Timer Register

4−29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.32

Asynchronous Request Filter High Register

4−30

. . . . . . . . . . . . . . . . . . . . .

4.33

Asynchronous Request Filter Low Register

4−32

. . . . . . . . . . . . . . . . . . . . .

4.34

Physical Request Filter High Register

4−33

. . . . . . . . . . . . . . . . . . . . . . . . . .

4.35

Physical Request Filter Low Register

4−35

. . . . . . . . . . . . . . . . . . . . . . . . . .

4.36

Physical Upper Bound Register (Optional Register)

4−35

. . . . . . . . . . . . . .

4.37

Asynchronous Context Control Register

4−36

. . . . . . . . . . . . . . . . . . . . . . . .

4.38

Asynchronous Context Command Pointer Register

4−37

. . . . . . . . . . . . . .

4.39

Isochronous Transmit Context Control Register

4−38

. . . . . . . . . . . . . . . . . .

4.40

Isochronous Transmit Context Command Pointer Register

4−39

. . . . . . . .

4.41

Isochronous Receive Context Control Register

4−39

. . . . . . . . . . . . . . . . . .

4.42

Isochronous Receive Context Command Pointer Register

4−41

. . . . . . . .

4.43

Isochronous Receive Context Match Register

4−42

. . . . . . . . . . . . . . . . . . .

5

GPIO Interface

5−1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

Serial ROM Interface

6−1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

Electrical Characteristics

7−1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1

Absolute Maximum Ratings Over Operating Temperature Ranges

7−1

.

7.2

Recommended Operating Conditions

7−2

. . . . . . . . . . . . . . . . . . . . . . . . . .

7.3

Electrical Characteristics Over Recommended Operating Conditions 7−3

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